1. Field of the Invention
The present invention relates to a semiconductor device and methods for manufacturing the same. The present invention particularly relates to a semiconductor device having a multilayer interconnection structure and a seal ring structure in which wires and via contacts surround a circuit section and also relates to a method for manufacturing such a device.
2. Description of the Related Art
The penetration of moisture into semiconductor packages causes the reliability of semiconductor devices to be seriously decreased. In general, semiconductor devices are formed on a wafer and the resulting wafer is diced into chips, which are formed into semiconductor packages. In this procedure, moisture can penetrate the chips through end faces thereof during or after the dicing operation.
In particular, when the semiconductor devices have a multilayer interconnection structure including interlayer insulating layers with low dielectric constant, the above problem is serious because such layers usually have low density and is therefore apt to suffer from moisture penetration.
In order to solve the problem, a seal ring structure has been proposed. The seal ring structure is defined as a ring-shaped wiring structure including wires and via contacts completely surrounding a circuit section. Seal rings extending through layers are formed together with internal wires and via contacts for forming the circuit section, and an additional photoresist step for forming seal rings is not therefore necessary. The resulting seal rings are vertically connected to each other. In the seal ring structure, since metal wires and insulating layers having high moisture resistance function as “barriers” that prevent moisture from penetrating the chips through end faces thereof, moisture can be prevented from penetrating the circuit section, which can therefore be prevented from being corroded.
FIG. 1 is a sectional view showing a first prior art semiconductor device having a single-damascene structure. The device is herein used for describing the penetration of moisture into the wiring structure. In the single-damascene structure, the following layers are disposed on a silicon substrate 1 in this order: an insulating layer 2 including elements, a first stopper layer 4, a first interlayer insulating layer 3, a second stopper layer 6, a second interlayer insulating layer 5, another first stopper layer 4, another first interlayer insulating layer 3, another second stopper layer 6, another second interlayer insulating layer 5, another first stopper layer 4, and another first interlayer insulating layer 3.
Wires 8, inside sealing wires 18, and outside sealing wires 28 extend through the first interlayer insulating layers 3 and first stopper layers 4. Via contacts 9, inside sealing via contacts 19, and outside sealing via contacts 29 extend through the second interlayer insulating layers 5 and second stopper layers 6. The wires 8 and via contact 9 form a circuit section 13, and the inside sealing wires 18, outside sealing wires 28, inside sealing via contacts 19, and outside sealing via contacts 29 form a seal ring section 12. The circuit section 13 is surrounded by the seal ring section 12.
With reference to FIG. 1, the wires 8 each lie on the corresponding via contacts 9, the inside sealing wires 18 each lie on the corresponding inside sealing via contacts 19, and the outside sealing wires 28 each lie on the corresponding outside sealing via contacts 29. That is, in the seal ring section 12, pairs of the inside sealing via contacts 19 and outside sealing via contacts 29 are alternately stacked and pairs of the inside sealing wires 18 and outside sealing wires 28 are alternately stacked.
Since the wires 8 and via contacts 9 are independently formed, the single-damascene structure necessarily has interfaces A–A′ between the first stopper layers 4 and second interlayer insulating layers 5 and interfaces B–B′ between the second stopper layers 6 and first interlayer insulating layers 3. These interfaces are flat and are each continuous with corresponding interfaces between the wires 8 and via-holes 9. Therefore, when moisture 11 penetrates the circuit section 13 from the outside, the moisture 11 passes through the first interlayer insulating layers 3, first stopper layers 4, second interlayer insulating layers 5, and second stopper layers 6 functioning as insulating layers and also travels along interfaces A–A′ and interfaces B–B′. Since the inside and outside sealing wires 18 and 28 fully extend through pairs of the first interlayer insulating layers 3 and first stopper layers 4 and the inside and outside sealing via-holes 19 and 29 fully extend through pairs the second interlayer insulating layers 5 and second stopper layers 6, the inside and outside sealing wires 18 and 28 and inside and outside sealing via-holes 19 and 29 completely intercept the moisture 11 passing through the insulating layers.
FIG. 2D shows a seal ring structure similar to the above structure. This seal ring structure is prepared according to steps shown in FIGS. 2A to 2D, which are sectional views.
With reference to FIG. 2D, the following layers are disposed on a silicon substrate 1 in this order: an insulating layer 2 including elements, a first interlayer insulating layer 21 containing a low dielectric material, a second interlayer insulating layer 22 containing silicon dioxide, and a third interlayer insulating layer 23 containing a low dielectric material. First metal wires 24 extend through the first interlayer insulating layer 21, second metal wires 25 extend through the second interlayer insulating layer 22 and third interlayer insulating layer 23, and via holes 20 extend through the second interlayer insulating layer 22. A seal ring 26 includes a first sealing layer 126, second sealing layer 226, and third sealing layer 326 that extend through the first, second, and third interlayer insulating layer 21, 22, 23, respectively.
FIGS. 2A to 2D are sectional views showing steps of forming the above components. As shown in FIG. 2A, the insulating layer 2 including the elements (not shown) such as transistors is formed on the silicon substrate 1. The first interlayer insulating layer 21 is then formed on the insulating layer 2. The first interlayer insulating layer 21 usually contains a low dielectric material so as to reduce the capacitance between wires.
As shown in FIG. 2B, a groove for forming the first sealing layer 126 and wiring grooves for forming wires are formed in the first interlayer insulating layer 21. Metal is deposited on the first interlayer insulating layer 21 such that the grooves are filled with the metal. An unnecessary metal layer, disposed on the first interlayer insulating layer 21, is removed by a CMP method, whereby the first metal wires 24 and first sealing layer 126 are formed.
The first sealing layer 126 has a width of about 1 μm and is placed at a position that is located close to a dicing line formed in a subsequent step and located about 10 μm apart from the circuit section 13 in the direction of the dicing line. Examples of a method for filling the grooves with the metal include a reflow process, CVD process, and plating process. In the reflow process, a metal layer is formed by a sputtering process and then melted by heat treatment. In general, examples of the metal include an aluminum alloy and copper.
As shown in FIG. 2C, the second interlayer insulating layer 22 is formed over the resulting first interlayer insulating layer 21 by a plasma CVD process and the third interlayer insulating layer 23 is then formed on the second interlayer insulating layer 22. The second interlayer insulating layer 22 contains silicon dioxide and the third interlayer insulating layer 23 contains a material similar to the low dielectric material contained in the first interlayer insulating layer 21. Silicon dioxide contained in the second interlayer insulating layer 22 has a relative dielectric constant of 4.4, which is greater than that of the low dielectric material.
As shown in FIG. 2D, the via holes 20 are formed in the second interlayer insulating layer 22, grooves are formed in the third interlayer insulating layer 23, and wiring grooves for forming the second and third sealing layers 226 and 326, which lie on the first sealing layer 126 in that order and have the same width as that of the first sealing layer 126, are formed in the second and third interlayer insulating layers 22 and 23, respectively. The via holes 20, grooves, and wiring grooves are filled with the metal according to the same procedure as that for forming the first metal wires 24, whereby the second metal wires 25 and second and third sealing layers 226 and 326 are formed. The first, second, and third sealing layers 126, 226, and 326, which are joined to one another, form the seal ring 26. The seal ring 26 seals the circuit section 13 from moisture coming from the direction of the first and second metal wires 24 and 25.
The steps shown in FIGS. 2C and 2D are then repeated several times, whereby the first and second metal wires 24 and 25 are stacked. In the final step, a passivation layer (not shown) is formed over the top surface, whereby a wafer process is completed. The obtained wafer is cut along dicing lines each extending outside the seal ring 26, that is, the wafer is diced into chips, each of which functions as the semiconductor device.
In the wafer having the above configuration, since the seal ring 26 containing the metal extends through the insulating layers and lies between each dicing line and the circuit section 13, moisture in the atmosphere can be prevented from penetrating the circuit section 13 through cut surfaces formed by cutting the wafer along the dicing lines. Since the first and second metal wires 24 and 25 of the circuit section 13 are placed in a plurality of the insulating layers and the sealing layers are placed in all of the insulating layers, moisture can be securely prevented from penetrating end faces of the semiconductor devices. This configuration is disclosed in, for example, Japanese Unexamined Patent Application Publication No. 2000-150429.
FIG. 3 is a sectional view showing a second prior art semiconductor device having a dual-damascene structure. The device is herein used for describing the penetration of moisture into the structure.
With reference to FIG. 3, the following layers are disposed on a silicon substrate 1 in this order: an insulating layer 2 including elements, a first stopper layer 4, and a first interlayer insulating layer 3. Pairs of second stopper layers 6 and second interlayer insulating layers 7 are disposed on the first interlayer insulating layer 3. Wires 14, via contacts, and sealing wires 10 extend through the second stopper layers 6 and second interlayer insulating layers 7.
In the dual-damascene structure, since the wires 14 and via contacts disposed thereunder are formed in one step, there are no interfaces A–A′ shown in FIG. 1 but there are only interfaces B–B′ between the second stopper layers 6 and second interlayer insulating layers 7 and interfaces B–B′ between the second stopper layers 6 and first interlayer insulating layer 3. Interfaces B–B′ are continuous with the interfaces between the via contacts and the sealing wires 10 or wires 14 disposed under the via contacts or connected to the interfaces between the via contacts and first, second, and third wires 8, 18, or 28 disposed under the via contacts. Moisture 11 can pass through the second stopper layers 6 and second interlayer insulating layers 7 and also travel along interfaces B–B′ between the second stopper layers 6 and second interlayer insulating layers 7 and interfaces B–B′ between the second stopper layers 6 and first interlayer insulating layer 3. Since the sealing wires 10 fully extend through pairs of the second stopper layers 6 and second interlayer insulating layers 7 in the vertical direction, the sealing wires 10 completely intercept the moisture 11 passing through the insulating layers.
However, in the above known examples in which only the seal rings extend across the insulating layers, the penetration of moisture cannot be completely prevented. In the structure shown in FIG. 1, since the adhesion of the wires to the via contacts is weak, the penetration of moisture, which travels along interfaces A–A′ between the first stopper layers 4 and second interlayer insulating layers 5 or interfaces B–B′ between the second stopper layers 6 and first interlayer insulating layers 3, cannot be completely prevented.
Furthermore, in the structure shown in FIG. 3, since the adhesion of the wires to the via contacts disposed thereon is weak, the penetration of moisture, which travels along interfaces B–B′ between the second stopper layers 6 and second interlayer insulating layers 7, cannot be completely prevented.